1. Field of the Invention
The present invention relates to a method and process for executing a selftest of a Random Access Memory (RAM) in an electronic device, especially a device such as a computer whose central processing unit (CPU) and arithmetic logic unit (ALU) are dependent on a stored program.
2. Background of the Prior Art
During the operation of a computer in flight critical or safety critical applications, only certain types of RAM fault modes can be selftested, and this testing is further limited as follows: When a cell or a small group of cells is tested consecutively, each access to these cells must be prohibited during the test, and interrupts to the CPU may be prohibited in order to decrease the total testing time; the shorter these prohibitions, the smaller the number of cells which can be tested during each test cycle and the longer the complete RAM test cycle. In actual practice, the test time as well as the interrupt inhibit time is arbitrarily limited to the number of cycles in which two 16-bit words, or with the most modern 32-bit microprocessors two 32-bit words can be tested. The realtime is calculated from the number of instructions based essentially on their execution times: two each Save, Store, Read, Restore instructions. Whether the crosstalk between neighboring cells can be tested during this short time depends on the RAM-architecture. In no case can a von Neumann programmed computer read cells which are not consecutively addressed quickly enough to either test the above mentioned crosstalk (because of the above mentioned access and interrupt inhibit) or to test the recovery times of the read amplifiers of the RAMs. To test the latter, consecutive cells must be read out with the maximum readout speed of the RAMs. By reading out the cells at the maximum speed via a von Neumann programmed computer, boundary conditions cannot be detected and random faults are not reliably detectable.
A critical RAM test is only possible by use of special test devices (testers), which can exercise read and write accesses at the maximum speed of the RAM. Integrated circuits have been introduced to the market lately which can overcome certain RAM faults via fault detection and correction facilities. This facility is only active when a RAM cell is accessed, and for an avionic computer requires a significant amount of extra fault detection and correction bits (e.g. according to the method of R. Hamming). The rapid selftests of the present invention would be unnecessary, since the fault statistics can be accumulated in the computer via software; these fault-statistics programs must be called after each fault occurence and this process could hinder the main program execution.